1. Technical Field
The present invention relates to a chip carrier (or chip) having an attached compliant layer of soft and spongy material, and associated method of fabrication, such that the compliant layer reduces thermally induced strains that would otherwise exist in solder joints that couple the chip carrier (or chip) to an electronic carrier such as a circuit card. The compliant layer acts as an interposer between the chip carrier (or chip) and the electronic carrier.
2. Related Art
An electronic assembly, such as a chip or chip carrier, is typically coupled to an electronic carrier, such as a circuit card, by a soldered interface. The soldered interface may include a conductive body such as a solder ball or a solder column. The resultant solder joints at the soldered interface are unfortunately subject to thermal stresses that occur during periods in which the electronic assembly/carrier configuration is heated or cooled. The thermal stresses, and consequent thermally induced strains, at the solder joints may arise from a mismatch in coefficient of thermal expansion (CTE) between the electronic assembly and the electronic carrier. For example, a circuit card made of epoxy, glass, etc. has a CTE of approximately 18 ppm/xc2x0C. In contrast, a ceramic chip carrier has a CTE of 3 to 6 ppm/xc2x0C. and an organic chip carrier has a CTE typically between 10 to 17 ppm/xc2x0C. Thus, thermal cycling with any of the preceding chip carriers and a circuit card is characterized by a materially greater rate of thermal expansion of the circuit card than the chip carrier. The thermal stresses and consequent strains resulting from the CTE mismatch during thermal cycling may cause fatigue failure in the solder joint at the soldered interface.
Another problem of thermally induced strain relates to large laminate carriers, such as large chip carriers, even where this is no mismatch of CTE. The problem arises from transient spatial effects in temperature, wherein the circuit card and regions of the chip carrier heat up or cool down at different rates during thermal cycling. Thus at a given time during a thermal transient, the circuit board and some regions of the chip carrier may be at different temperatures. If xcex94T is the maximum temperature difference between the circuit board and the chip carrier at a given instant of time, the maximum differential rate of thermal expansion between the circuit card and the chip carrier at the given time, in units of ppm, is proportional to the product of CTE and xcex94T. Thus, thermal strains may be induced because of xcex94T between different locations even if CTE does not vary between the different locations. Since the magnitude of xcex94T during thermal cycling has a propensity to increase with increasing surface area of the chip carrier, it follows that thermally induced strain, due to xcex94T, tends to increase with increasing surface area of the chip carrier. While this xcex94T problem may be tolerable with conventional chip carriers having typical dimensions of about 32 mmxc3x9732 mm, the xcex94T problem is of concern with larger chip carriers having dimensions of about 50 mmxc3x9750 mm and larger. Thus, problems of thermally induced strain may be caused by a CTE mismatch, an unacceptably high xcex94T in large chip carriers, or both.
A known and commonly used method of solving the aforementioned CTE problem is using long solder columns at the soldered interface. By distributing the total thermal stress over a long element, the local unit thermal stress is correspondingly reduced. The long solder columns would also mitigate the aforementioned problem of high xcex94T between the chip carrier and the circuit card. A difficulty with long solder column approach, however, is that long solder columns introduce unwanted inductance into the electronic circuits, thereby degrading electronic performance.
A method is needed for solving the aforementioned problems of thermally induced stains such that electronic performance is not degraded.
The present invention discloses an electrical structure, comprising:
a substrate; and
a compliant layer having a plated through hole (PTH), wherein a top surface of the compliant layer is attached to a bottom surface of the substrate at a first electrical contact, and wherein the PTH electrically couples the first electrical contact to a second electrical contact located on the bottom surface of the compliant layer.
The present invention also provides a method for forming an electrical structure, comprising the steps of:
providing a substrate;
providing a compliant layer;
forming a plated through hole (PTH) through the compliant layer;
forming a top pad on a top surface of the compliant layer, wherein the top pad is electrically coupled to the PTH;
forming a bottom pad on a bottom surface of the compliant layer, wherein the bottom pad is electrically coupled to the PTH;
applying a mask layer to the bottom surface of the compliant layer, wherein the mask layer covers the bottom pad and an end of the PTH; joining the compliant layer with the substrate, mechanically and electrically at the top pad; and
removing a portion of the mask layer, wherein a portion of the bottom pad is exposed.
The present invention has the advantage of relieving thermal stress at a soldered interface between an electronic assembly (such as a chip or chip carrier) and an electronic carrier (such as a circuit card) without introducing unwanted inductance. Thus the present invention reliably solves the thermal stress problem without adversely affecting electronic performance.
The present invention has the advantage of mitigating thermally induced bending stresses, despite the fact that the compliant layer of the present invention introduces an asymmetry in compliance and/or temperature, about the centerline of a chip carrier.
The present invention has the advantage of allowing users of ceramic substrates to continue to use ceramic substrates instead having to expend resources to switch to other materials having a CTE that is more favorable than the CTE of a ceramic substrate.